Fernando Martínez Santa ¹, Fredy H. Martinez Sarmiento ¹, Holman Montiel Ariza ¹

Affiliations
1 Technological Faculty, District University Francisco Jose de Caldas, Bogota D. C, CO

Abstract

Objectives: To design and implement a totally-functional 4-bit didactic processor, in order to be applied as a tool for improving the learning process of students of microprocessors courses, and to be used as a base for future applications. Methods/Analysis: This work was reached through the application of a final course project in microprocessor and digital circuit courses, where it was given to the students via web platform, just the basic block diagram (to use Bottom- Up methodology) and they had to complete or design collaboratively the rest of details or blocks which is necessary to work. This processor was implemented using hardware description languages such as: Very fast speed Hardware Description Language (VHDL) and Verilog, on Complex Programmable Logic Device (CPLD) and Field Programmable Gate Array (FPGA). Findings: The present one is used as a teaching tool for digital circuits and microprocessor courses in the Technology Faculty of District University (Bogotá, Colombia). This minimalist design of the processor was done to reduce the amount of resultant digital gates, in order to implement inside a small digital programmable device. As a result, it was obtained as a simple processor to start with the basic concepts in the learning process of micro-processors and a little improvement of final exams results due to the involving of students into real problems as collaborative designers. Novelty/ Improvements: Reduced design is capable to implement on small CPLD or to be implemented sometimes on FPGA to do parallel applications. Additionally, its reduced size helps to easily understand it and implementing by the students.

Keywords

4-bit Processor, Didactic Processor, Finite State Machine, Harvard, RISC, VHDL, Verilog, Processor Design

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Fernando Martínez Santa ¹, Edwar Jacinto Gomez ¹, Holman Montiel Ariza ¹

Affiliations
1 Universidad Distrital Francisco Jose de Caldas, Bogota D.C, CO

Abstract

Objectives: To propose an algorithm for global optimized path planning for mobile robots on static and observable environments, based on image skeleton technique and using some other image processing algorithms. Methods/Analysis: The proposed geometric scheme is supported on the skeletonization of image of free space into a navigation environment, as a strategy to limit the number of possible paths from a starting to end points for a mobile robot. This approach, considerably simplifies the selection of appropriate paths, allows defining lines (edges) that can be utilized by graphs for the specification of paths. Several simulation and real test were done to prove the efficiency of the algorithm. For the real test, a prototype differential platform was build using a LEGO Mindstorms NXT robotics kit. Findings: The strategy demonstrated excellent performance and robustness over about 50 simulations and experimental tests, finding always a feasible and short path., but taking in average 6.4 seconds to find the solution. Novelty/Improvements: The proposed algorithm showed to work better than other tested algorithms like Voronoi and Bug, especially when the navigation environment is a maze.

Keywords

Deep Search, Hybrid Scheme, Image Skeletonization, Navigation, Path Planning, Robotics

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Julio Enrique Rodríguez Prieto ¹, Edwar Jacinto Gómez ¹, Fernando Martínez Santa ¹

Affiliations
1 Technological Faculty, Universidad Distrital Francisco José de Caldas, Bogotá D.C., CO

Abstract

Objectives: To design an 8-bit RISC microcontroller in VHDL and implement it on an FPGA, taking as a reference the mid-range microcontroller core of Microchip 16FXXX. Methods/Analysis: This microcontroller has been designed using modular blocks and correspond Harvard-type architecture. It has a stack of eight levels and an Arithmetic Logic Unit (ALU) for operations with 8-bit data and bit-oriented instructions. Also, it has a program memory of 8Kx14-bit and a data memory of 512x8-bit. The number of storage locations of these memory modules is easily scalable and/or modified as needed by the designer due to high abstraction level which has been used in its description. Similarly, the other blocks (as well as the microcontroller in general) are easily modified, providing a modular system resulting in excellent versatility to be adapted to be additional modules including: input and output ports, timers, blocks for communication among others. Findings: The proposed device has an instruction OPCODE correspondent to PIC16FXX processor core, so the system can be programmed with the same machine language. It also presents a high support for compilers such as MPASM (Microchip Assembler) and CCS PIC-C (C language). The compatibility with the C compiler is quite interesting, making easy the development of large-scale digital designs, thanks to the existence of extensive libraries in this programming language. Novelty/ Improvements: The system provides the enough user support. A document was generated with all data and instructions that the designer needs to take into account for executing or modifying the microcontroller design. This support, along with the open source firmware, was published on the Internet, so that communities can access it, adopt it and/or modify it.

Keywords

Embedded Microcontroller, FPGA, Harvard Architecture, SoftCore, VHDL

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